Patent
B. Yuce, N. F. Ghalaty, P. Schaumont, Technique for Recovering the Fault-Free State of Micro-processors, U.S. Patent Application No: 62/340,613.
Book Chapter
N. F. Ghalaty, B. Yuce, P. Schaumont, A Systematic Approach to Fault Attack Resistant Design, S.Bhunia, S. Ray and S. Sur-Kolay [Editors], Fundamentals of IP and SoC Security-Design Verification and Debug, Springer International Publishing, New York, USA.
Journal Articles
N. F. Ghalaty, P. Schaumont, An Automated Tool for Eliminating and Analyzing Fault Sensitivity Analysis, Under development to be submitted to IEEE Embedded Systems Letters.
Yuce, B., Ghalaty, N.F., Deshpande, C., Santapuri, H., Patrick, C., Nazhandali, L. and Schaumont, P., 2017. Analyzing the fault injection sensitivity of secure embedded software. ACM Transactions on Embedded Computing Systems (TECS), 16(4), p.95.
H. Farbeh, N. Mirzadeh, N. F. Ghalaty, S.G. Miremadi, M. Fazeli, H. Asadi, A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, V. 24, Issue 11, pp 3296-3309.
N. F. Ghalaty, B. Yuce, P. Schaumont, Analyzing the Eciency of Biased-Fault Based Attacks, IEEE Embedded Systems Letters , Top 50 popular articles in IEEE ESL, 8(2),pp 33-36.
Peer Reviewed Conference and Workshop Proceedings
C. Zhi, J. Shen, A. Nicolau, A. Veidenbaum, N. Farhady, R. Cammarota. , CAMFAS: A Compiler Approach to Mitigate Fault Attacks via Enhanced SIMDization." In 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), pp. 57-64. IEEE, 2017.
Z. Ghaderi, N. F. Ghalaty, Low Overhead DVFS-based PUF, Under development to be submitted to2nd International Verification and Security Workshop (IVSW), Feb. 2017.
C. Patrick, B. Yuce, N. F. Ghalaty, P. Schaumont, Lightweight Fault Attack Resistance in Software Using Intra-Instruction Redundancy, Selected Areas in Cryptography (SAC), St. John's, Canada, 2016.
B. Yuce, N. F. Ghalaty, H. Santapuri, C. Deshpande, C. Patrick, P. Schaumont, Software Fault Resistance is Futile: Effective Single-glitch Attacks, Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), Santa Barbara, CA, 2016.
C. Deshpande, B. Yuce, N. F. Ghalaty, D. Ganta, P. Schaumont, L. Nazhandali, A Congurable and Lightweight Timing Monitor for Fault Attack Detection, IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, PA, 2016.
B. Yuce, N. F. Ghalaty, C. Depande, C. Patrick, L. Nazhandali, P. Schaumont, FAME: Fault-attack Aware Microprocessor Extensions for Hardware Fault Detection and Software Fault Response, Proceedings of the Fifth Workshop on Hardware and Architectural Support for Security and Privacy,2016.
N. F. Ghalaty, B. Yuce, L. Nazhandali, P. Schaumont, FAME: Fault-Attack Awareness using Microprocessor Enhancements, Winner of Best Paper in Session Award, Semiconductor Research Corporation Techcon, Austin, TX, 2015.
B. Yuce, N. F. Ghalaty, P. Schaumont, Improving Fault Attacks on Embedded Software using RISC Pipeline Characterization, Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), Saint Malo, France, 2015, pp. 97-108.
N. F. Ghalaty, B. Yuce, P. Schaumont, Dierential Fault Intensity Analysis on PRESENT and LED Block Ciphers, Constructive Side-Channel Analysis and Secure Design, 2015, Berlin, Germany, pp. 174-188. Springer International Publishing.
B. Yuce, N. F. Ghalaty, P. Schaumont, TVVF: Estimating the Vulnerability of Hardware Cryptosystems against Timing Violation Attacks, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington, DC, 2015, pp. 72-77.
N. F. Ghalaty, B. Yuce, M. Taha, P. Schaumont, Dierential Fault Intensity Analysis, Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), Busan, South Korea, 2014, pp. 49-58.
N. F. Ghalaty, A. Aysu, P. Schaumont, Analyzing and Eliminating the Causes of Fault Sensitivity Analysis, Design, Automation and Test in Europe Conference and Exhibition (DATE), Dresden, Germany, 2014, pp. 1-6.
A. Aysu, N. F. Ghalaty, Z. Franklin, M. P. Yali, P. Schaumont, Digital Fingerprints for Low-Cost Platforms using MEMS Sensors, Proceedings of the Workshop on Embedded Systems Security, Quebec, Canada, 2013, pp. 1-6. ACM.
S.N. Ahmadyn, M. Fazeli, N. F. Ghalaty, S.G. Miremadi, Value-Aware Low-Power Register File Architecture, Winner of Best Paper Award, 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS), Shiraz, Fars, 2012, pp. 44-49.
N. F. Ghalaty, M. Fazeli , H. Izadirad, S.G. Miremadi, Software-Based Control Flow Error Detection and Correction Using Branch Triplication, 2011 IEEE 17th International On-Line Testing Symposium (IOLTS), Athens, Greece, 2011, pp. 214-217.
Poster Presentations
A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction ISCAS-17
FAME: Fault Attack Awareness Using Microprocessor Enhancements CHES-16
DFIA: The Earth in Fault Attack Universe, Winner of Best Poster Award CESCA-15
Fault Sensitivity Analysis, Causes and Countermeasures DAC-14
New Directions in Fault Attacks: FSA & DFIA, Winner of Best Presentation Award CESCA-14
Fault Attacks and Countermeasures by Delay Balancing CRAW-14
